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pr eliminary this is a product that has fixed target specifications but are subject ramtron international corporation to change pending characterization results . 1850 ramtron drive, colorado springs, co 80921 (800) 545 - fram, (719) 481 - 7000 http://www.ramtron.com rev. 1.0 mar. 2012 page 1 of 14 fm 25e 64 64kb serial low energy f - ram memory features 64k bit ferroelectric nonvolatile ram ? organized as 8,192 x 8 bits ? high endurance 1 tr i llion (10 1 2 ) read/writes ? 36 year data retention at +75oc ? nodelay? writes ? advanced high - reliability ferroelectric process fa st spi interface ? up to 20 mhz frequency ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) ? software write - protection (bp bits) ? hardware write - pr otect (/wp pin) active - low reset input ? holds device in reset state while power supply stabilizes ? reduces time to first f - ram access ? allows freedom of power supply ramp rates low voltage/ low energy consumption ? vdd = 1.8v 0.1v ( - 1 version) ? vdd = 1.5v + 0.1 5 v , - 0.1v ( - 2 version ) ? 2 0 ? a (typ.) active current at 1 mhz ? 0.1 ? a (typ.) standby current industry standard configuration ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green/rohs soic package description the fm 25 e64 is a low voltage, low energy 64 - kilobit nonvolatile memory employing an advanced f - ram process . it provides reliable data retention for 36 years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolati le memories. t he fm 25 e64 performs write operations at bus speed. no write delays are incurred. data is written to the m emory array immediately after each byte has been successfully transferred to the device. the next bu s cycle may commence immediately without the need for data polling . in addition, the product offers substantial write endurance compared with other nonvolatile memories. the fm 25 e64 is capable of supporting 10 1 2 read/write cycles, or amillion times more write cycles than eeprom . these c apabilities make the fm 25 e64 ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of eeprom can cause data loss. the fm 25 e64 provides substantial benefits to users of serial eeprom as a hardware drop - in replacement. the fm 25 e64 uses the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. device specifi cations are guaranteed over an industrial temper ature range of - 40c to +85c. pin configuration pin name function /cs chip select sck serial clock si serial data input so serial data output /rst reset input /wp write protect input vdd supply voltage vss ground c s s o w p v s s v d d r s t s c k s i 1 2 3 4 8 7 6 5 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 2 of 14 figure 1. block diagram pin descriptions pin name i/o description /rst input reset input: this active - low p in is used to hold the memory in a reset state while power is being stabilized. when /rst is low, the interface is inactive and the spi state machine is reset. once vdd is within spec, the /rst pin may be driven high. the memory is ready for commands within t pu . /cs input chip select: this active low input activates the device. when high, the devic e enters low - power standby mode and ignores other inputs. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sck input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge . since the device is static, the clock frequency may be any value between 0 and 20 mhz and may be interrupted at any ti me. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. so output serial output: this is the data output pin. it is driven during a read and remains tri - stated at all other times including when /rst is low. data transitions are driven on the falling edge of the serial clock. /wp input write protect: this active low pin prevents write operations to the status register only. a complete explanation of write p rotection is provided on pages 7 and 8 . vdd supply power supply vss supply ground i n s t r u c t i o n d e c o d e c l o c k g e n e r a t o r c o n t r o l l o g i c w r i t e p r o t e c t i n s t r u c t i o n r e g i s t e r a d d r e s s r e g i s t e r c o u n t e r 1 , 0 2 4 x 6 4 f r a m a r r a y 1 3 d a t a i / o r e g i s t e r 8 n o n v o l a t i l e s t a t u s r e g i s t e r 3 c s s c k s o s i r s t www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 3 of 14 overview the fm 25 e64 is a low energy serial f - ram memory. the memory array is logically organized as 8,192 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the f - ram is similar to serial eeproms. the major difference between the fm 25 e64 and a serial eeprom with the same pinout is the f - ram s superior write performance. memory architecture when accessing the fm 25 e64 , the user addresses 8,192 locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using th e spi protocol, whic h includes a chip select , an op - code, and a two - byte address. the upper 3 bits of the address range are dont care values. the complete address of 13 - bits specifies each byte address uniquely. most functions of the fm 25 e64 either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained in mor e detail in the interface section. users expect several obvious system benefits from the fm 25 e64 due to its fast write cycle and high endurance as compared to eeprom. in applications that have a limited power budget, the fast - write and low - power operatio n provides a much lower energy solution for nonvolatile store compared to eeprom since the access is completed quicker and at a very low voltage. by contrast, an eeprom requires milliseconds to perform a write operation and at much higher currents. reset a reset input (/rst ) is provided a s a means to hold the memory interface in a reset state during power cycle events . when /rst is driven low, the memory enter s a reset condition. in this state, the interface is locked out and the so pin is high impedance. when /rst is driven high, the memory enters a normal operating mode after the t pu time is satisfied . driving /rst low during a read or write operation will abort the operation and data may be lost . note: the fm 25 e64 contains no power management circuits . t o ensure proper operation , the user is responsible for /rst being held active (low) while v dd voltage stabilizes and is within the specified dc min/max limits . it is recommended that the part is not powered down with chip enable active. serial periphera l interface C spi bus the fm 25 e64 employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 20 mhz. this high - speed serial bus provides high performance serial communication to a host microcontroller. many common microcont rollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm 25 e64 operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, d ata - in, data - out, and chip select. a typical system configuration uses one or more FM25E64 devices with a microcontroller that has a dedicated spi port, as figure 2 illustrates. note that the clock, data - in, and data - out pins are common among all devices. the chip select pin must be driven separately for each FM25E64 device. for a microcontroller that has no dedicated spi bus, a ge neral purpose port may be used. figure 3 shows a configur ation that uses the mcu gpio pins. www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 4 of 14 figure 2. system configuration with spi port figure 3. system configuration without spi port protocol overview the spi interface is a synchronous serial interface using clock and data pins. once chip select is activated by the bus master, the fm 25 e64 will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device will make a determination of the spi mode on the falling edge of eac h chip select. while there are four suc h modes, the fm 25 e64 supports m odes 0 and 3. figure 4 shows the req uired signal relationships for m odes 0 and 3. for both modes, data is clocked into the fm 25 e64 on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protocol is controlled by op - codes. these op - codes specify the commands to th e device. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. importa nt: t he /cs pin must go inactive after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select. s p i m i c r o c o n t r o l l e r f m 2 5 e 6 4 s o s i s c k c s s c k m o s i m i s o s s m o s i : m a s t e r o u t s l a v e i n m i s o : m a s t e r i n s l a v e o u t s s : s l a v e s e l e c t s y s t e m r e s e t r s t m i c r o c o n t r o l l e r f m 2 5 e 6 4 s o s i s c k c s p 1 . 0 p 1 . 1 p 1 . 3 s y s t e m r e s e t r s t p 1 . 2 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 5 of 14 spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 4. spi modes 0 & 3 power up to first access the fm25 e64 is not accessible for a period of time (t pu ) after power up. users must comply with the timing parameter t pu , which is the minimum time from /rst deasserted to the first /cs low. data transfer all data transfers to and from the fm 25 e64 occur in 8 - bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb ) first. serial inputs are registered on the rising edge of s ck. outputs are driven from the falling edge of sck. command structure there are six commands called op - codes that can be issued by the bus master to the fm 25 e64 . they are listed in the table b elow. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are com mands followed by one byte, either in or out. they operate on the status register . the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op - code commands name description op - code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b wren C set write enable latch the fm 25 e64 will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the status register (wrsr) and writing the memory (write). 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 6 of 14 sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit C only the wren op - code can set this bit. the wel bit will be automatically cleared on the rising edge of /cs following a wrdi, a wrsr, or a write operation. this prevents further writes to the sta tus register or the f - ram array without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi C write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus timing figure 6. wrdi bus timing rdsr C read status register the rdsr command allows the bus master to verify the contents of the status register . reading status provides information about the current state of the write protection features. following the rdsr op - code, the fm 25 e64 will return one byte with the contents of the status register . the status register is described in detail in a l ater section. wrsr C write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register . prior to issuing a wrsr command, the /wp pin must be high or inactive. note that on the fm 25 e 64 , /wp only prevents writing to the status register , not the memory array. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. cs sck si so 0 1 2 3 4 5 6 7 0 0 0 0 0 1 1 0 c s s c k s i s o 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 7 of 14 figure 7. rdsr bus timing figure 8. wrsr bus timing (wren not shown) status register & wr ite protection the write protection features of the fm 25 e64 are multi - tiered . a wren op - code must be issued prior to any write operation . assuming that writes are enabled using wren, writes to memory are controlled by the status register . as described above, writes to the status register are performed using the wrsr command and subject to the /wp pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 6 are fixed at 0 and can not be modified. note that bit 0 ( ready in eeproms) is unnecessary as the f - ram writes in real - time and is never busy. the wpen, bp1 and bp0 control write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the st ate of the write enable latch. attempting to directly write the wel bit in the status regist er has no effect on its state . this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify po rtions of memory that are write - protected as shown in the following tab le. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 1800h to 1fffh (upper ?) 1 0 1000h to 1fffh (upper ?) 1 1 0000h to 1fffh (all) the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware / wp pin. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register . thus the status register is write protected if wpen=1 and /wp=0. c s s c k si so c s s c k s i s o 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 1 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 8 of 14 this scheme provides a write protection mechanism, which can p revent software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is set to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware p revents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f - ram technology. unlike spi - bus eeproms, the fm 25 e64 can perform sequential writes at bus speed. no page register is needed and any numbe r of sequential writes may be performed. write operation all writes to the memory begin with a wren op - code with /cs being asserted and deasserted. the next op - code is write. the write op - code is follow ed by a two - byte address value. the upper 3 - bits of the address are ignored. in total, the 13 - bits specify the address of the first data byte of the write operation. this is the starting address of the first data byte of the write operation. subsequent bytes are data bytes, which are written sequentially. a ddresses are incremented internally as long as the bus master continues to issue clocks and keeps /cs low. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is written msb first. the rising edge of /cs terminates a write op eration. a write operation is shown in figure 9. eeproms use page buffers to increase their write throughput. this compensates for the technologys inherently slow write operations. f - ram memories do not have page buffers because each byte is written to the f - ram array immediately after it is clocked in (after the 8 th clock). this allows any number of bytes to be written without page buffer delays. figure 9. memory write (wren not shown) read operation after the falling edge of /cs, the bus master can issue a read op - code. following the read command is a two - byte address value. the upper 3 - bits of the address ar e ignored. in total, the 13 - bits specify the address of the first byte of the read operation. this is the starting address of the first byte of the read operation. after the op - code and address are issued, the device drives out the read data on the next 8 clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and /cs is low. if the last address of 1fff h is reached, the counter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read operation. a read operation is shown in figure 10. 0 1 2 3 4 5 6 7 0 1 2 3 4 5 o p - c o d e 0 0 0 0 0 0 1 0 m s b 1 3 - b i t a d d r e s s 10 9 6 x x x 12 11 c s s c k si so 7 8 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 7 6 5 4 3 2 1 0 l s b m s b l s b d a t a www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 9 of 14 figure 10. memory read endurance the fm 25 e64 devices are capable of being accessed at least 10 1 2 times, reads or writes. an f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f - ram architecture is based on an array of rows and columns. rows are defined by a12 - a3 and column addresses by a2 - a0. see block diagram (pg 2) which shows the array as 1k rows of 64 - bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the table below shows endurance calculations for a system that has a repeating loop to the f - ram. suppose that the mcu polls (reads or writes) th e f - ram at a constant repeat rate for the lifetime of the product . the routine accesses the same locations every time the loop is run. this causes each byte to experience one endurance cycle through the loop. f - ram read and write endurance is virtually un limited even for loops that repeat ot a 1ms rate . table 5. time to reach endur ance limit for repeating loop cycle time of repeating loop endurance cycles/sec. endurance cycles/year years to reach limit (10 12 ) 1 ms 10 00 3.15 x 10 10 31.7 5 ms 2 0 0 6.30 x 10 9 158.7 2 0 ms 5 0 1.58 x 10 9 634.9 0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 0 0 1 m s b 1 3 - b i t a d d r e s s x x x 1 2 1 1 1 0 4 3 2 1 0 7 6 5 4 3 2 1 0 l s b m s b l s b c s s c k s i s o d a t a 1 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 10 of 14 electrical specifica tions absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +2.4 v v in voltage on any pin with respect to v ss - 1.0v to +2.4 v and v in < v dd + 0 .7 v t stg storage temperature - 55 ? c to + 12 5 ? c t lead lead temperature (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) tbd tbd tbd package moisture sensitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating c onditions ( t a = - 40 ? c to + 85 ? c, unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage FM25E64 - 1 FM25E64 - 2 1. 7 0 1.4 0 1. 8 1.5 1. 9 0 1.6 5 v v i dd 1 vdd supply current (FM25E64 - 1) @ sck = 1.0 mhz @ sck = 20.0 mhz 20 400 5 0 900 a a 1 i dd2 vdd supply current (FM25E64 - 2) @ sck = 1.0 mhz @ sck = 20.0 mhz 20 300 40 600 a a 1 i sb standby current FM25E64 - 1 FM25E64 - 2 - - 0. 1 0.1 5 3 ? a ? a 2 i li input leakage current - ? 1 ? a 3 i lo output leakage current - ? 1 ? a 3 v ih input high voltage 0.7 5 v dd v dd + 0.3 v v il input low voltage - 0.3 0.25 v dd v v oh output high voltage @ i oh = - 1 ma v dd C 0. 3 - v v ol output low voltage @ i ol = 1 ma - 0. 2 v notes 1. sck toggling between v dd - 0.2 v and v ss , other inputs v ss or v dd - 0.2 v. so=open. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v ss ? v in ? v dd and v ss ? v out ? v dd . www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 11 of 14 ac parameters ( t a = - 40 ? c to + 85 ? c , c l = 30pf , unless otherwise specified ) symbol parameter min max units notes f ck sck clock frequency 0 20 mhz t ch clock high time 22 ns 1 t cl clock low time 22 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable time 20 ns 2 t odv output data valid time 20 ns t oh output hold time 0 ns t d deselect time 60 ns t r data in rise time 50 ns 2,3 t f data in fall time 50 ns 2,3 t su data setup time 5 ns t h data hold time 5 ns notes 1. t ch + t cl = 1/f ck . 2. characterized but not 100% tested in production. 3. rise and fall times measured b etween 10% and 90% of waveform. capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 1.6 v) symbol parameter min max units notes c o output c apacitance (so) - 8 pf 1 c i input c apacitance - 6 pf 1 notes 1. this parameter is periodically sampled and not 100% tested. ac test conditions input pulse levels 10% and 90% of v dd input rise and fall times 5 ns input and out put timing levels 0.5 v dd output load capacitance 30 pf data retention symbol parameter min max units notes t dr @ +85oc 10 - years @ +80oc 18 - years @ +75oc 36 - years www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 12 of 14 serial data bus timing power cycle timing power cycle timing ( t a = - 40 ? c to + 85 ? c , unless otherwise specified ) symbol parameter min max units notes t pu /rst high to first access start 1 0 - ? s t pd last access complete to v dd (min) 0.2 - ? s t v r v dd rise time 1 - ? s/v 1 t vf v dd fall time 1 - ? s/v 1 t rh /rst hold time after v dd (min) at power up 0 - ? s t rs /rst setup time to v dd (min) at power down 0 - ? s notes 1. this parameter is guaranteed by design . c s s c k s i s o 1 / t c k t c l t c h t c s h t o d v t o h t o d t c s u t s u t h t d t r t f v d d m i n t p u v d d c s t v r t p d t v f r s t t r h t r s www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 13 of 14 mechanical drawing 8 - pin soic (jedec ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: x x x xx x x= part number, p= package type ( g=soic ) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm 25 e64 - 1 , green soic package, year 2012 , work week 1 7 fm 25 e64 1 g es a 00002g1 ric12 1 7 xxx x x xxp rll llll l ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 ? 0 . 40 1 . 27 0 . 19 0 . 25 0 ? - 8 ? recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70 www.datasheet.co.kr datasheet pdf - http://www..net/
FM25E64 - 64kb 1.5v & 1.8v spi f - ram rev. 1.0 mar. 2012 page 14 of 14 revision history revision date summary 1 .0 3/ 16 / 2012 initial release ordering information part number operating voltage package fm 25e 64 - 1 g 1.8v (0.1v) green 8 - pin soic fm 25e 64 - 1 gtr 1.8v (0.1v) green 8 - pin soic, tape & reel fm 25e 64 - 2 g 1.5v (+0.15v, - 0.1v) green 8 - pin soic fm 25e 64 - 2 gtr 1.5v (+0.15v, - 0.1v) green 8 - pin soic, tape & reel www.datasheet.co.kr datasheet pdf - http://www..net/

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